This invention relates to metal lines of an integrated circuit (IC), and more particularly relates to spacing metal lines in an integrated circuit to minimize capacitive issues along speed sensitive pathways in a random access memory structure to reduce signal delay without negatively impacting Werner Fill processing.
The Werner Fill process is disclosed by commonly owned U.S. Pat. No. 5,981,384, the disclosure of which is herein fully incorporated by reference. The Werner Fill process modifies the layout of electrically unisolated or live metal lines so that the spacing between the metal lines is substantially standardized prior to performing deposition of an intermetal dielectric layer (IDL). According to the Werner Fill process, circuit layout design modifications are made by adding dummy metal line features in areas of the layout having open spaces between parallel metal lines, and adding metal line spacers to existing metal lines to reduce the spacing therebetween to a standardized spacing or gap. As the nonstandard spacing between metal lines becomes standardized to the standardized spacing or gap, an intermetal dielectric deposition results in a planarized surface of the intermetal dielectric. Consequently, many conventional process steps for planarizing the intermetal dielectric can be skipped or simplified.
However, as semiconductor device geometries continue to decrease in size, providing more devices per fabricated wafer, capacitance between metal line features (dummy and/or live) becomes an issue. Currently, some devices are being fabricated with spacing between metal line features of less than about 0.25 μm, and in some cases, the spacing between metal line features is as little as about 0.11 μm. Since delay of a signal through a metal line is directly proportional to capacitance, and capacitance is inversely proportional to spacing, further reductions in spacing will cause increases in capacitance, and thus substantial signal delay. This increased signal delay along long, substantially parallel metal lines features, which typically are speed sensitive pathways, has noticeably affected the other desire in the art to provide faster semiconductor devices. Accordingly, a need still exists to minimize capacitive issues (i.e., increased capacitance) along speed sensitive pathways in a random access memory structure to reduce signal delay without negatively impacting the Werner Fill process.